By Iwai H., Shur M.S., Nishi Y.
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7 3. Scaling Beyond 90 nm A number of companies have announced the elements of their 65 nm node technology. e. ). At the device level, device performance enhancement of 15-30% as compared to 90 nm has been reported. It remains to be seen how much of the device enhancement can be translated to the enhanced chip performance. Because of higher density, unless the technology has noticeable device enhancement and the variability is under control, it is very difficult to obtain chip level performance gain, especially for high power chips in 90 nm technology.
Figure 9 shows the variation of the threshold voltage with back-gate bias for various TG geometries. The coupling effect VT{VG2) i s clearly reinforced for wider fins 3D Size Effects in Advanced SOI Devices 23 400 350 > S 300 00 B 250 o 2 200 I 150 "-15 -10 -5 0 Back gate voltage (V) 5 Fig. 9. Threshold voltage versus substrate bias in triple-gate FinFETs with different aspect ratio (tsi/W = 20/80 ran (wide fin), 20/20 nm (square fin), 80/20 nm (tall fin). (W = 80nm and tSi = 20nm), suggesting that the classical ID vertical coupling16 between the front channel and the back gate prevails.
An ultimate and more unusual size effect is related to the transistor volume. FinFET technology will soon be capable of delivering devices with all dimensions (thickness, width, length) in the 10-20 nm range. A 10 _ 1 8 cm 3 body volume raises interesting fundamental questions. For example, what doping level one single impurity can induce? Does the impurity position matter? Or, should atomistic simulations include all silicon atoms? 24 S. Cristoloveanu et al. (b) Swing = 75mV/decade FinFET domain yP'\ - r i-gate cr' _H> i 20 40 60 80 Fin width W (nm) 100 15 D- D i i FDSOI 20 25 30 Channel length L Q (nm) 35 Fig.