Nonvolatile Memory Technologies with Emphasis on Flash: A by Joe Brewer, Manzur Gill

By Joe Brewer, Manzur Gill

Offered here's an all-inclusive remedy of Flash expertise, together with Flash reminiscence chips, Flash embedded in common sense, binary phone Flash, and multilevel cellphone Flash. The publication starts with an educational of uncomplicated options to orient readers who're much less acquainted with the topic. subsequent, it covers all features and diversifications of Flash expertise at a mature engineering point: easy gadget buildings, ideas of operation, comparable method applied sciences, circuit layout, total layout tradeoffs, machine checking out, reliability, and functions.

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Extra resources for Nonvolatile Memory Technologies with Emphasis on Flash: A Comprehensive Guide to Understanding and Using Flash Memory Devices (IEEE Press Series on Microelectronic Systems)

Example text

It was not until 1988 when the reliability of the emerging devices was proven that volume production really began [8], and that structure, named ETOX (Intel trademark) for EPROM tunnel oxide [9], became an industry standard Flash cell. The ETOX device had a tunnel oxide thickness of about 10 nm, a graded source junction, and an abrupt drain junction. 5 V. Programming was done by CHE. The ETOX type of cell has been employed dominantly for NOR arrays. Historically, NAND arrays have employed a similar transistor structure, but the simple daisy chain interconnection of individual transistors to form a string allows the sharing of interconnection overhead over 8, 16, or 32 cells resulting in a much smaller area per bit.

Reading or writing processes must be designed such that unselected cells are not disturbed while the selected cells are operated on. The design of the array must contend with basic circuit design issues associated with driving heavily loaded transmission lines as well as assuring proper operation of each individual cell. In order to select a given row and column an integrated memory device is usually provided with a binary address word from external circuitry. The address word is routed to address decoder circuitry that is tightly tied to the sides of the array, and designed to drive the word and bitlines.

It is important that the distribution of threshold voltages for the programmed state be limited to a specified design range in order to assure proper circuit operation. There are a number of basic principles of operation that apply to both NOR and NAND organized devices. For a single read operation the individual bits that form a word are made to appear in an input/output register. For a single write operation the word present in an input/output register is used to determine the data inserted into the cells for that word.

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